Shenzhen Sai Collie Technology Co., Ltd.

Shenzhen Sai Collie Technology Co., Ltd.

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XC3S400A-4FGG320C IC Chip Programming Wide Frequency Range FPGA 1.14V

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Shenzhen Sai Collie Technology Co., Ltd.
City:shenzhen
Country/Region:china
Contact Person:DANDAN
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XC3S400A-4FGG320C IC Chip Programming Wide Frequency Range FPGA 1.14V

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Brand Name :XILINX / AMD
Model Number :XC3S400A-4FGG320C
Place of Origin :original
MOQ :1
Price :Negotiable
Payment Terms :L/C, D/A, D/P, T/T, Western Union, MoneyGram
Supply Ability :999999
Delivery Time :1 - 3 days
Packaging Details :standard
Mounting Type :Surface Mount
Operating Temperature :-40°C ~ 100°C (TJ)
Number of I/O :251
Voltage - Supply :1.14V ~ 1.26V
Package / Case :320-BGA
Supplier Device Package :320-FBGA (19x19)
PN :XC3S400A-4FGG320C
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View Product Description
XC3S400A-4FGG320C Programmable
IC Chip 320-FBGA Package Wide Frequency Range FPGA

Number of LABs/CLBs
896
Number of Logic Elements/Cells
8064
Total RAM Bits
368640
Number of I/O
251
Number of Gates
400000
Voltage - Supply
1.14V ~ 1.26V
Mounting Type
Operating Temperature
0°C ~ 85°C (TJ)
Package / Case
Supplier Device Package
320-FBGA (19x19)
Base Product Number

XC3S400A-4FGG320C

• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 502 I/O pins or 227 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• Selectable output drive, up to 24 mA per pin


• QUIETIO standard reduces I/O switching noise
• Full 3.3V ± 10% compatibility and hot swap compliance
• 640+ Mb/s data transfer rate per differential I/O
• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors
• Enhanced Double Data Rate (DDR) support
• DDR/DDR2 SDRAM support up to 400 Mb/s


• Fully compliant 32-/64-bit, 33/66 MHz PCI® technology support
• Abundant, flexible logic resources
• Densities up to 25,344 logic cells, including optional shift register or distributed RAM support
• Efficient wide multiplexers, wide logic
• Fast look-ahead carry logic
• Enhanced 18 x 18 multipliers with optional pipeline


• IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
• Up to 576 Kbits of fast block RAM with byte write enables for processor applications
• Up to 176 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)


• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 320 MHz)

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XC3S400A-4FGG320C IC Chip Programming Wide Frequency Range FPGA 1.14V

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